NANOCONTROLLER PROGRAM OPTIMIZATION USING ITE DAGS

Kentucky Architecture nanocontrollers employ a bit-serial SIMD-parallel hardware design to execute MIMD control programs. A MIMD program is transformed into equivalent SIMD code by a process called Meta-State Conversion (MSC), which makes heavy use of enable masking to distinguish which code should be executed by each processing element. Both the bit-serial operations and the enable masking imposed on them are expressed in terms of if-then-else (ITE) operations implemented by a 1-of-2 multiplexor, greatly simplifying the hardware. However, it takes a lot of ITEs to implement even a small program fragment. Traditionally, bit-serial SIMD machines had been programmed by expanding a fixed bitserial pattern for each word-level operation. Instead, nanocontrollers can make use of the fact that ITEs are equivalent to the operations in Binary Decision Diagrams (BDDs), and can apply BDD analysis to optimize the ITEs. This thesis proposes and experimentally evaluates a number of techniques for minimizing the complexity of the BDDs, primarily by manipulating normalization ordering constraints. The best method found is a new approach in which a simple set of optimization transformations is followed by normalization using an ordering determined by a Genetic Algorithm (GA)

Manipulating MAXLIVE For Spill-Free Register Allocation

Abstract. Many embedded systems use single-chip microcontrollers which have no on-chip RAM. In such a system, the processor registers must hold all live data values. Nanocontrollers further reduce the controller circuit complexity so that a nanocontroller can be embedded with each of thousands to millions of sensors, actuators, or other devices on a single chip. This reduction in circuit complexity is accomplished by using a bit-serial multiplexorbased SIMD architecture with just tens of one-bit local registers. These registers not only must hold all declared and temporary values, but also are used to hold program state information in support of MIMD programmability. Implementing word-level operations using bit-serial multiplexor operations often yields huge basic blocks with very complex DAGs, apparently requiring even more registers. Spilling is not possible, so code that needs too many registers simply cannot be run. This paper explores new compilation methods, including Genetic Algorithms (GAs) and a new adaptation of Sethi-Ullman numbering, to aggressively restructure the code and allocate registers so that the number of nanocontroller registers used does not exceed the number available. The approach also is shown to be adaptable to solve the less demanding problem of avoiding register spills for microcontrollers or general-purpose processors.